1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit device provided with a plurality of memory cells each including a capacitor and each having a voltage input node and a storage node at opposite sides of the capacitor, respectively and more particularly, to a semiconductor integrated circuit device in which by utilizing coupling effect of the capacitor, a period required for performing a data retention test can be shortened.
2. Description of the Prior Art
When write or read is performed on a plurality of memory cells each including a capacitor, a word line of a selected one of the memory cells is set to high level from low level within a withstand voltage range of 2.7 to 3.6V in the case of a supply voltage of 3V and within a withstand voltage range of 1.6 to 2.3 V in the case of a supply voltage of 1.8V such that an access transistor is turned on. During write, desired low-level or high-level data on a bit line for write is transmitted to a storage node via the access transistor. On the other hand, during read, desired low-level or high-level data stored in the storage node of the memory cell is transmitted to the bit line through the access transistor.
Meanwhile, also outside the withstand voltage range, the memory cell should have a property for retaining data, namely, a data retention property. In case the memory cell has the data retention property, data stored in the memory cell is retained without being contaminated even if a supply voltage of, for example, 3V drops to 2V outside a withstand voltage range of 2.7 to 3.6V. In this case, data written within the withstand voltage range of 2.7 to 3.6V is still retained even at 2V outside the withstand voltage range and can be read within the withstand voltage range.
In an inspection prior to shipment of semiconductor products employing memory cells, a data retention test is performed so as to check whether or not the memory cells have the data retention property. In order to reduce manufacturing costs of the semiconductor products, it is desirable that a period required for performing the data retention test is reduced as much as possible.
However, in a conventional memory cell, even if a supply voltage drops below a withstand voltage range, high level of a storage node does not drop immediately. This is because not only electric charge of the storage node leaks to only a power source but a load transistor leading to the power source has a very high resistance value. As a result, in an inspection prior to shipment of conventional semiconductor products employing memory cells, the period required for performing the data retention test becomes long disadvantageously.
Thus, in order to shorten waiting time of the data retention test, Japanese Patent Laid-pen Publication No. 5101649 (1993), for example, proposes that a parasitic capacity is added between a plate acting as a reference level of the capacitor and the power source. However, this prior art document is different from the present invention in that the prior art document requires addition of the parasitic capacity.
Accordingly, an essential object of the present invention is to provide, with a view to eliminating the above mentioned drawbacks of prior art a semiconductor integrated circuit device in which high level of a storage node of a memory cell is lowered sharply by coupling effect of a capacitor of the memory cell such that a period required for performing a data retention test can be shortened
In order to accomplish this object of the present invention, a semiconductor integrated circuit device according to the present invention includes a plurality of memory cells each of which includes a capacitor and has a voltage input node and a storage node at opposite sides of the capacitor, respectively. A first voltage generating circuit generates a first voltage. A second voltage generating circuit generates a second voltage lower than the first voltage. A switching circuit receives the first and second voltages and changes over the first and second voltages in response to a control signal so as to output the first and second voltages to the voltage input node in a normal operation mode and a data retention test mode, respectively.